We’re excited to share a demonstration of our dataflow architecture overlay on an FPGA. The workflow showcases the potential of our technology to simplify high-performance computing tasks.

In the demonstration, our system:

1. Loads a dataflow architecture binary onto the FPGA overlay.

2. Transfers the program for the dataflow machine overlay along with input data.

3. Executes the program, which squares an array of numbers from 0 to 127.

Including the time for loading, computation, and printing results, the entire process takes only 0.3 seconds!

Click here to read the full post from Jinho.