The Initial Working Version on FPGA!

Key Highlights:

• Scratchpad Memory (SPM): I added a 4KB SPM using BRAM to provide faster and more accessible data storage for the design.

• Test Case: To verify the functionality, I initialized the SPM with integers from 0 to 1023 and squared each value using the computation units in my design.

• Dataflow Graph Execution:The dataflow graph (as illustrated below) was directly fed to the hardware in its binary form without any optimizations, such as execution scheduling.The hardware autonomously determined how to execute the graph in a massively parallel fashion.

• Outcome: The FPGA processed the graph and returned squared integers (0², 1², 2², ..., 1023²) in real-time, demonstrating the functionality of the first version!

Click here to read the full development log from Jinho!